In a PC Motherboard, The Motherboard’s busses are regulated by a number of controllers.Generally, these are small circuits which have been designed to look after a particular job, like moving data to and from EIDE Devices (i.e hard disks, etc).So, as there are many different types of hardware devices which all need to be able to communicate with each other, a number of controllers are needed on a motherboard & Thus, Most of these Controller-Functions were grouped together into a couple of large chips, which together comprised the Chipset Architecture.
In Olden Days, In the Motherboard’s Chipset Architecture, Intel’s Earlier Chipset generally became an efficient & in-expensive way to bring a large number of powerful features into the Personal-Computers that require the highest performance by controlling the various Interfaces as well as its connections between the CPU (i.e Processor) & the Flash-BIOS.
Thus, Due to the difficulty of integrating all components onto a single chipset, this Intel’s Earlier Chipset were broken down into a Multi-Tier Architecture known as North-Bridge/South-Bridge Architecture which was further divided into 2 Components i.e North-Bridge & South-Bridge.
This North-Bridge & South-Bridge were connected by a powerful Internal-Bus called a“Link-Channel” where these two chips manage communications between the CPU and other parts of the motherboard by sharing the work of managing the data-traffic, and constitute the core logic chipset of the PC Motherboard.
Fig.No.01: North-Bridge Mounted on Motherboard.
1) In the Motherboard’s Chipset Architecture, one of the Most Important Chip among the North-Bridge/South-Bridge Architecture in the Core-Logic Chipset on the PC-Motherboard is called as North-Bridge.
2) This North-Bridge is not only a highest-speed component of the Chipset but also a principal-device typically responsible for the interfacing of CPU, Main-Memory/RAM, Local AGP Graphics Slots & controlling the flow of data between the CPU, RAM & AGP Port for handling communications among them.
3) Thus, this North-Bridge In-Directly controls the flow of data from the CPU to the RAM & AGP Port with the help of the Main-Memory/RAM Slots & Local AGP Graphics Slots,& to transmit/receive the data sent to and fro from the CPU, RAM & AGP Port to the Flash-BIOS it establishes a 4-way connection between the CPU, RAM & AGP Port & the South-Bridge by Connecting:
a) The CPU to itself by a FSB ( i.e Front-Side Bus) of 3.2 GB/s Bandwidth.
b) The Main-Memory/RAM Slots to itself by a Dual-Channel Memory-Bus of 1.6GB/s Bandwidth.
c) The Local AGP Graphics Slots to itself by a Local AGP Bus of 266 MB/s Bandwidth.
d) & by Connecting the South-Bridge (ICH) to itself by a Link-Channel known as Internal-Bus of 266 MB/s Bandwidth.
4) Thus, this North-Bridge is usually slightly larger than the South-Bridge, it is kept at a closest distance to the CPU (i.e Processor) and Main-Memory, so that whenever the CPU needs data from RAM, a request can be sent to the Memory-Controller of the North-Bridge & after the request has been received, it responds with “how long the processor needs to wait to read the memory over the Front-Side Bus (FSB)”.
5) Thus, The Speed of the Processor becomes Faster due to a very large amount of Data-Traffic passed in a Very-High Frequency & so this North-Bridge generally gets more hotter, Therefore to Control its Temperature & provide more cooling, A Big Heat-Sinker is attached to it.
6) Therefore, the Major-Advantages of having the North-Bridge integrated on the CPU Die is that, “it reduce the amount of time taken by a packet of data to traverse from the CPU to Main-Memory (i.e Latency)”.
Fig.No.02: North-Bridge/South-Bridge Chipset Architecture
Fig.No.03: South-Bridge Mounted on Motherboard.
1) In the Motherboard’s Chipset Architecture, the Secondmost Important Chip among the North-Bridge/South-Bridge Architecture in the Core-Logic Chipset on the PC-Motherboard is called as South-Bridge.
2) This South-Bridge is the lowest-speed component of the Chipset typically responsible for Controlling the Operations of transfer of data to & fro from the Harddisk to all the other Input/Output as well as Peripheral-Devices by handling all of the less performance-critical I/O function capabilities, such as the IDE channels, SATA , USB, Ethernet, Audio-Codec, and Fire-Wire etc which is connected to the System’s Flash ROM (BIOS) by the LPC Bridge.
3) Thus, During the Data-Transfer Process between the HDDs to all other I/O & Peripheral Devices, for the Data Control & Access the northbridge directly link signals from the I/O units to the CPU with the help of CICC( i.e Controller Integrated Channel Circuitry), which is connected to the North-Bridge by a Link-Channel known as Internal-Bus of 266 MB/s Bandwidth.
4) Since, the I/O Ports & Buses generally operate at a far slower speed than the FSB connected to the CPU by the North-Bridge, an external system-support is been provided by a device through the South-Bridge by implementing the slower capabilities of the Motherboard in a Northbridge/Southbridge Chipset Architecture Known as “SUPER I/O” .
5) This “SUPER I/O” device consist of various system support for the I/O Ports & Buses which incorporates a set of number of different controller functions like:
|a) LPC Bridge.||b) SPI-Bus.|
|c) SM-Bus.||d) DMA-Controller.|
|e) Interrupt-Controllers.||f) Mass Storage Controllers.|
|g) Real-time Clock.||h) Power-Management (APM & ACPI).|
|i) Non-Volatile BIOS Memory.||j) AC’97 or Intel’s High Definition Audio Sound Interface.|
|k) Out-of-Band Management Controller (i.e BMC or HECI).|
Lets see one by one in detail:
a) LPC Bridge:
The LPC Bridge provides a Data & Control-Path to the Super I/O (The Normal-Attachment for the Keyboard, Mouse, Parallel-Port, Serial-Port, IR-Port, and Floppy-Controller) & FWH (Firm-Ware HUB) which provides access to BIOS Flash-Storage.
The SPI-Bus is a simple Serial-Bus mostly used for FWH.
The SM-Bus is used to communicate with other devices on the Motherboard (e.g System-Temperature Sensors, Fan-Controllers).
The DMA-Controller allows ISA/LPC Devices to directly access the Main-Memory without needing help from the CPU.
The Interrupt-Controller provides a mechanism for attached devices to get attention from the CPU.
f) Mass Storage Controllers:
This typically allows Direct-Attachment of System Hard-Drives by PATA and/or SATA.
g) Real-time Clock:
The real time clock provides a Persistent Time-Account.
h) Power-Management (APM & ACPI):
The APM or ACPI functions provide methods and signaling to allow the computer to sleep or shut down to save power.
i) Non-Volatile BIOS Memory:
The System CMOS (BIOS Configuration Memory), assisted by the Supplemental Battery-Power, creates a Limited Non-Volatile Storage-Area for System-Configuration Data.
j) AC’97 or Intel’s High Definition Audio Sound Interface.
k) Out-of-Band Management Controller such as a BMC or HECI.